Verification by error modeling: using testing techniques in hardware verification
Auteur :
Radecka, Katarzyna / Zilic, Zeljko
Éditeur :
Springer-Verlag New York Inc.
ISBN :
9781441954022
Date de publication :
7 déc. 2010
Dimensions :
23,5 x 15,5 cm
Langue :
Anglais
Pays d'origine :
USA
Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.