Logic synthesis and verification algorithms
Auteur :
Hachtel, Gary D. / Somenzi, Fabio
Éditeur :
Springer-Verlag New York Inc.
ISBN :
9781475770360
Date de publication :
18 mars 2013
Dimensions :
25,4 x 17,8 cm
Langue :
Anglais
Pays d'origine :
USA
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).