Wafer level reliability of advanced cmos devices & processes
Éditeur :
Nova Science Publishers Inc
ISBN :
9781604567137
Date de publication :
26 nov. 2008
Dimensions :
18,0 x 26,0 cm
Poids :
608 g
Langue :
Anglais
Pays d'origine :
USA
The definition from SEMATECH of wafer level reliability test is a methodology to assess the reliability impact of tools and processes by testing mechanism-specific test structures under accelerated conditions during device processing. This book discusses items of wafer level reliability of CMOS devices and processes.