Digital timing macromodeling for vlsi design verification
Auteur :
Kong, Jeong-Taek
Éditeur :
Kong, Jeong-TaekOverhauser, David V.,
ISBN :
9780792395805
Date de publication :
1 mai 1995
Dimensions :
23,4 x 15,6 x 1,7 cm
Poids :
586 g
Format :
Laminated cover
Langue :
Anglais
Pays d'origine :
USA
Presents the history of the development of simulation techniques. This work features discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods.