Pipelined multi-core mips machine, a: hardware implementation and correctness proof
Auteur :
Kovalev, Mikhail / Müller, Silvia M. / Paul, Wolfgang J.
Éditeur :
Springer International Publishing AG
ISBN :
9783319139050
Date de publication :
1 déc. 2014
Dimensions :
23,5 x 15,5 cm
Langue :
Anglais
Pays d'origine :
Suisse
It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory.