Logic synthesis and soc prototyping: rtl design using vhdl
Auteur :
Taraate, Vaibbhav
Éditeur :
Springer Verlag, Singapore
ISBN :
9789811513169
Date de publication :
30 janv. 2021
Dimensions :
23,5 x 15,5 cm
Langue :
Anglais
Pays d'origine :
Singapour
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.