Asic design and synthesis: rtl design using verilog
Auteur :
Taraate, Vaibbhav
Éditeur :
Springer Verlag, Singapore
ISBN :
9789813346413
Date de publication :
7 janv. 2021
Dimensions :
23,5 x 15,5 cm
Langue :
Anglais
Pays d'origine :
Singapour
This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.